The present invention relates generally to semiconductor devices and methods of manufacture, and more particularly, to semiconductor devices and methods of manufacture including a trenched gate.
Conventional semiconductor non-volatile memories, such as read-only memories (ROMs), erasable-programmable ROMs (EPROMs), electrically erasable-programmable ROMs (EEPROMs), and flash EEPROMs are typically constructed using a double-poly structure. Referring now to FIG. 1, there is shown a cross-sectional view of the device structure of a conventional nonvolatile memory device 100 including a substrate 102 of a semiconductor crystal such as silicon. The device 100 also includes a channel region 104, a source region 106, a drain region 108, a floating gate dielectric layer 110, a floating gate electrode 112, an inter-gate dielectric layer 114, and a control gate electrode 116. The floating gate dielectric layer 110 isolates the floating gate electrode 112 from the underlying substrate 102 while the inter-gate dielectric layer 114 isolates the control gate electrode 116 from the floating gate electrode 112. As shown in FIG. 1, the floating gate dielectric layer 110, the floating gate electrode 112, the inter-gate dielectric layer 114, and the control gate electrode 116 are all disposed on the surface of the substrate 102. The device structure of conventional non-volatile memory devices as shown in FIG. 1 is limited to the degree to which the active devices can be made smaller in order to increase device packing density and performance. Additionally, the stacked dual gate structure which is formed on the substrate surface is sensitive to process variations of overlaps between the floating gate and the source and drain junctions.
In accordance with the present invention, a non-volatile semiconductor device is fabricated to include a trenched floating gate and a control gate. Embodiments employing the principles of the present invention improve the device scaleability and packing density by reducing the lateral diffusion of the source and drain regions under the trenched floating gate. The corner-limiting lateral diffusion of the source and drain regions under the trenched floating gate also minimizes the process variations of overlaps between the trenched floating gate and the source and drain regions. Moreover, the present invention reduces the stacked gate height of the structure thus providing better process control and manufacturability. Furthermore, a device fabricated according to the principles of the present invention can be more efficiently programmed and erased than conventional non-volatile devices.
In one embodiment of the present invention, a device structure for a non-volatile semiconductor device includes a trenched floating gate and a control gate. The trenched floating gate is formed in a trench etched into a semiconductor substrate. The device structure further includes a source region, a drain region, and a channel region which is implanted in the substrate beneath the bottom surface of the trench. An inter-gate dielectric layer is formed on a top surface of the trenched floating gate, and the control gate is fabricated on the inter-gate dielectric layer.
In another embodiment, a device structure fabricated according to the principles of the present invention comprises a trenched floating gate, a control gate, and sidewall dopings. The sidewall dopings are formed in a semiconductor substrate having a trenched floating gate and laterally separate the trench in which the trenched floating gate is formed from the source and drain regions. The sidewall dopings are immediately contiguous the vertical sidewalls of the trench and immediately contiguous the substrate surface. The sidewall dopings reduce the coupling between the control gate and the source and drain regions and reduce leakages from the vertical sides of the trench in which the trenched floating gate is formed. Furthermore, the sidewall dopings of the present invention enhance the program and erase efficiency of the non-volatile device by contributing to higher electrical fields around the bottom corners of the gate trench where program and erase operations take place when compared to the electrical fields of prior art devices.
In accordance with one embodiment of the present invention, a trenched floating gate semiconductor device with sidewall dopings is fabricated by first etching a trench in the silicon substrate and implanting the substrate with dopant impurities to form a channel region beneath the trench. The sidewall dopings are then formed by implanting the substrate at an angle with dopant impurities. After the sidewall dopings have been formed in the substrate, a trench-to-gate insulating layer is formed inside the trench followed by the layer of polysilicon to form the trenched floating gate. The polysilicon layer is planarized until it is substantially planar with the substrate surface. An inter-gate dielectric layer is then formed on the top surface of the trenched floating gate. Next, a control gate is fabricated on the inter-gate dielectric layer, and control gate spacers are formed at the vertical side surfaces of the control gate. Finally, source and drain regions are implanted into the substrate.